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Impact of device scaling on deep sub-micron transistor reliability : a study of reliability trends using SRAM

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dc.contributor.author White, Mark
dc.contributor.author Huang, Bing
dc.contributor.author Qin, Jin
dc.contributor.author Gur, Zvi
dc.contributor.author Talmor, Michael
dc.contributor.author Chen, Yuan
dc.contributor.author Heidecker, Jason
dc.contributor.author Nguyen, Duc
dc.contributor.author Bernstein, Joseph
dc.date.accessioned 2009-03-19T17:57:00Z
dc.date.available 2009-03-19T17:57:00Z
dc.date.issued 2005-10-17
dc.identifier.citation 2005 IEEE International Integrated Reliability Workshop Final Report, October 17-20, 2005, doi:10.1109/IRWS.2005.1609574 en_US
dc.identifier.clearanceno 05-3085
dc.identifier.uri http://hdl.handle.net/2014/41138
dc.description.abstract As microelectronics are scaled in to the deep sub-micron regime, users of advanced technology CMOS, particularly in high-reliability applications, should reassess how scaling effects impact long-term reliability. An experimental based reliability study of industrial grade SRAMs, consisting of three different technology nodes, is proposed to substantiate current acceleration models for temperature and voltage life-stress relationships. This reliability study utilizes step-stress techniques to evaluate memory technologies (0.25mum, 0.15mum, and 0.13mum) embedded in many of today's high-reliability space/aerospace applications. Two acceleration modeling approaches are presented to relate experimental FIT calculations to Mfr's qualification data. en_US
dc.description.sponsorship NASA/JPL en_US
dc.language.iso en_US en_US
dc.publisher IEEE en_US
dc.subject CMOS integrated circuits en_US
dc.subject SRAM chips en_US
dc.subject embedded systems en_US
dc.subject integrated circuit modelling en_US
dc.subject integrated circuit reliability en_US
dc.title Impact of device scaling on deep sub-micron transistor reliability : a study of reliability trends using SRAM en_US
dc.type Article en_US


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