|
BEACON eSpace at Jet Propulsion Laboratory >
JPL Technical Report Server >
JPL TRS 1992+ >
Please use this identifier to cite or link to this item:
http://hdl.handle.net/2014/9461
|
| Title: | Validation of an SEU simulation technique for a complex processor: PowerPC7400 |
| Authors: | Swift, G.M.
Rezgui, S.
Velazco, R. |
| Issue Date: | 15-Jul-2002 |
| Citation: | NSREC 2002
Phoenix, AZ, USA |
| Abstract: | Published data on the processors sensitivites with respect to SEU is generally obtained from radiation ground testing during which the program is executed by the DUT consists in the sequential inspection of each of the processor memory cells accessible to the user, through the execution of a suitable instruction sequence. In such programs, so-called static tests, typically considered memory cells are general-purpose registers, special registers (program counter, stack pointer...) and internal memory. Nevertheless, the register use and duty cycle of the final application will be very different, including using instructions no in the static tests and disturbing other potential SEU targets. The ideal would be the use of the final application program for the radiation ground testing, but generally this program is either unknown or unavailable when the qualification testing is performed on candidate circuits to space projects. |
| URI: | http://hdl.handle.net/2014/9461 |
| Appears in Collections: | JPL TRS 1992+
|
Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.
|
