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Title: FY11 End of Year Report NEPP SOC Devices
Authors: Guertin, Steven M.
Keywords: Freescale P2020
System on a Chip
single event effects
L1 cache
L2 cache,
Issue Date: Mar-2012
Publisher: Pasadena, CA : Jet Propulsion Laboratory, National Aeronautics and Space Administration, 2011.
Series/Report no.: JPL Publication
Abstract: This is the final report for fiscal year (FY) 2011 NEPP System-on-a-Chip (SOC) Devices task. This task seeks to provide improved methods for SOC testing to the NASA community, with the goal of providing data that is of interest to NASA and that meets the standards of the wider radiation-effects community. This report describes continued efforts to establish qualification and radiation testing methods appropriate to SOC devices. This NEPP task seeks to understand the impact of radiation effects on devices of interest to NASA programs. Because SOC devices are combinations of several types of computer circuit elements, many types of test approaches are applicable for the various elements of the devices. The current work is part of a multi-year effort to establish test methods based on examination of existing methods, development of new methods, and in-the-field verification of methods by radiation-testing SOCs of interest.
Appears in Collections:JPL TRS 1992+

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