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Please use this identifier to cite or link to this item: http://hdl.handle.net/2014/42143

Title: High-Density 3D TSOP Stack Packaging NEPP FY11 Summary Report
Authors: Phillip, Zulueta
Keywords: electronics
packaging
microelectronics
interconnect
devices
Issue Date: Feb-2012
Publisher: Pasadena, CA : Jet Propulsion Laboratory, National Aeronautics and Space Administration, 2012.
Series/Report no.: JPL Publication
12-2
Abstract: This report documents a reliability evaluation of a particular implementation of package-on-package (PoP) high-density electronic packaging technology. Package-on-package is just one of several new high density packaging technologies that offer significant reductions in overall required PCB board area while allowing for significant and often unique increases in device performance and functionality. The particular PoP technology tested for this report was provided by Interconnect Systems, Inc. (ISI). ISI utilizes standard, readily available device packaging methods in which high-density packaging is achieved through a combination of several
URI: http://hdl.handle.net/2014/42143
Appears in Collections:JPL TRS 1992+

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