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Title: Users guide on scaled CMOS reliability : NASA Electronic Parts and Packaging (NEPP) Program Office of Safety and Mission Assurance
Authors: White, Mark
Cooper, Mark
Johnston, Allan
Keywords: Scaling
Scaled CMOS
Issue Date: Nov-2011
Publisher: Pasadena, CA : Jet Propulsion Laboratory, National Aeronautics and Space Administration, 2011.
Series/Report no.: JPL Publication
Abstract: Reliability of advanced CMOS technology is a complex problem that is usually addressed from the standpoint of specific failure mechanisms rather than overall reliability of a finished microcircuit. A detailed treatment of CMOS reliability in scaled devices can be found in Ref. 1; it should be consulted for a more thorough discussion. The present document provides a more concise treatment of the scaled CMOS reliability problem, emphasizing differences in the recommended approach for these advanced devices compared to that of less aggressively scaled devices. It includes specific recommendations that can be used by flight projects that use advanced CMOS. The primary emphasis is on conventional memories, microprocessors, and related devices.
Appears in Collections:JPL TRS 1992+

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