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Please use this identifier to cite or link to this item:
http://hdl.handle.net/2014/41405
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| Title: | Reliability of low-pitch, high-I/O area array packages |
| Authors: | Ghaffarian, Reza |
| Keywords: | solder joint reliability
ball grid array
plastic ball grid arrays (PBGAs)
thermal cycle
chip scale packages (CSPs)
microlead frame (MLF)
x-ray
failure |
| Issue Date: | Apr-2009 |
| Publisher: | Pasadena, CA : Jet Propulsion Laboratory, National Aeronautics and Space Administration, 2009. |
| Series/Report no.: | JPL Publication
09-15 |
| Abstract: | This report first provides a body of knowledge (BoK) survey for designing, manufacturing, and testing high-input/output (I/O) and low-pitch area array packages. It then presents test data on design, assembly, and environmental evaluation results for various newly available electronics packages assembled onto printed wiring boards (PWBs). Packages included plastic ball grid arrays (PBGAs) with I/Os up to 1156 and 1-mm pitch, high-I/O chip scale packages (CSPs), low-pitch flip chip, microlead frame/quad flat no lead (MLF/QFN), and small resistors to 0201 size. Finally, it summarizes lessons learned from test results for assembly and environmental testing along with optical, scanning electron microscopy (SEM), and x-ray photomicrographs showing damage progress. |
| URI: | http://hdl.handle.net/2014/41405 |
| Appears in Collections: | JPL TRS 1992+
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