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Please use this identifier to cite or link to this item: http://hdl.handle.net/2014/41138

Title: Impact of device scaling on deep sub-micron transistor reliability : a study of reliability trends using SRAM
Authors: White, Mark
Huang, Bing
Qin, Jin
Gur, Zvi
Talmor, Michael
Chen, Yuan
Heidecker, Jason
Nguyen, Duc
Bernstein, Joseph
Keywords: CMOS integrated circuits
SRAM chips
embedded systems
integrated circuit modelling
integrated circuit reliability
Issue Date: 17-Oct-2005
Publisher: IEEE
Citation: 2005 IEEE International Integrated Reliability Workshop Final Report, October 17-20, 2005, doi:10.1109/IRWS.2005.1609574
Abstract: As microelectronics are scaled in to the deep sub-micron regime, users of advanced technology CMOS, particularly in high-reliability applications, should reassess how scaling effects impact long-term reliability. An experimental based reliability study of industrial grade SRAMs, consisting of three different technology nodes, is proposed to substantiate current acceleration models for temperature and voltage life-stress relationships. This reliability study utilizes step-stress techniques to evaluate memory technologies (0.25mum, 0.15mum, and 0.13mum) embedded in many of today's high-reliability space/aerospace applications. Two acceleration modeling approaches are presented to relate experimental FIT calculations to Mfr's qualification data.
URI: http://hdl.handle.net/2014/41138
Appears in Collections:JPL TRS 1992+

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