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Please use this identifier to cite or link to this item: http://hdl.handle.net/2014/41046

Title: A re-programmable platform for dynamic burn-in test of Xilinx Virtexll 3000 FPGA For military and aerospace applications
Authors: Roosta, Ramin
Wang, Xinchen
Sadigursky, Michael
Tracton, Phil
Keywords: dynamic burn in
Field Programmable Gate Arrays (FPGA)
Issue Date: 8-Sep-2004
Publisher: Pasadena, CA : Jet Propulsion Laboratory, National Aeronautics and Space Administration, 2004.
Citation: 7th International Conference on Military and Aerospace Programmable Logic Devices (MAPLD), Washington, D.C., September 8-11, 2004
Abstract: Field Programmable Gate Arrays (FPGA) have played increasingly important roles in military and aerospace applications. Xilinx SRAM-based FPGAs have been extensively used in commercial applications. They have been used less frequently in space flight applications due to their susceptibility to single-event upsets. Reliability of these devices in space applications is a concern that has not been addressed. The objective of this project is to design a fully programmable hardware/software platform that allows (but is not limited to) comprehensive static/dynamic burn-in test of Virtex-II 3000 FPGAs, at speed test and SEU test. Conventional methods test very few discrete AC parameters (primarily switching) of a given integrated circuit. This approach will test any possible configuration of the FPGA and any associated performance parameters. It allows complete or partial re-programming of the FPGA and verification of the program by using read back followed by dynamic test. Designers have full control over which functional elements of the FPGA to stress. They can completely simulate all possible types of configurations/functions. Another benefit of this platform is that it allows collecting information on elevation of the junction temperature as a function of gate utilization, operating frequency and functionality. A software tool has been implemented to demonstrate the various features of the system. The software consists of three major parts: the parallel interface driver, main system procedure and a graphical user interface (GUI).
URI: http://hdl.handle.net/2014/41046
Appears in Collections:JPL TRS 1992+

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