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Title: Optimizations of a hardware decoder for Deep-Space optical communications
Authors: Cheng, Michael K.
Nakashima, Michael A.
Moision, Bruce E.
Hamkins, Jon
Keywords: Cyclic redundancy check (CRC)
field-programmable gate array (FPGA) implementation
optical communications
quadratic polynomial interleaver
turbo decoding
Issue Date: 2-Mar-2007
Publisher: IEEE
Citation: IEEE Transactions On Circuits and Systems—I: Regular Papers, Vol. 55, NO. 2, March doi:200810.1109/TCSI.2007.913733
Abstract: The National Aeronautics and Space Administration has developed a capacity approaching modulation and coding scheme that comprises a serial concatenation of an inner accumulate pulse-position modulation (PPM) and an outer convolutional code [or serially concatenated PPM (SCPPM)] for deep-space optical communications. Decoding of this code uses the turbo principle. However, due to the nonbinary property of SCPPM, a straightforward application of classical turbo decoding is very inefficient. Here, we present various optimizations applicable in hardware implementation of the SCPPM decoder. More specifically, we feature a Super Gamma computation to efficiently handle parallel trellis edges, a pipeline-friendly “maxstar top-2” circuit that reduces the max-only approximation penalty, a low-latency cyclic redundancy check circuit for window-based decoders, and a high-speed algorithmic polynomial interleaver that leads to memory savings. Using the featured optimizations, we implement a 6.72 megabits-per-second (Mbps) SCPPM decoder on a single field-programmable gate array (FPGA). Compared to the current data rate of 256 kilobits per second from Mars, the SCPPM coded scheme represents a throughput increase of more than twenty-six fold. Extension to a 50-Mbps decoder on a board with multiple FPGAs follows naturally. We show through hardware simulations that the SCPPM coded system can operate within 1 dB of the Shannon capacity at nominal operating conditions.
Appears in Collections:JPL TRS 1992+

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