spacer spacer spacer
NASA Logo - Jet Propulsion Laboratory + View the NASA Portal
JPL Home Earth Solar System Stars & Galaxies Technology
Jet Propulsion
Laboratory

BEACON eSpace at Jet Propulsion Laboratory >
JPL Technical Report Server >
JPL TRS 1992+ >

Please use this identifier to cite or link to this item: http://hdl.handle.net/2014/40761

Title: Disturb testing in flash memories
Authors: Sheldon, Douglas
Freie, Michael
Keywords: NASA Electronic Parts and Packaging (NEPP)
NAND flash devices
multi-level cell (MLC) NAND
Issue Date: Mar-2008
Publisher: Pasadena, CA : Jet Propulsion Laboratory, California Institute of Technology, 2008
Series/Report no.: JPL Publication
08-07
Abstract: Non-volatile memory technology as defined by NAND architecture flash memory continues to lead the process scaling and device shrinking efforts of the entire integrated circuit industry. 45- nm technology nodes are now producing commercial 32Gb devices. These latest 32Gb devices are pioneering new charge trapping memory cell technologies using metal gates and high-k dielectric materials. These cells are called TANOS and consist of tantalum-nitride, aluminum oxide (high k material), nitride, oxide, and silicon. Such high-density memories continue to revolutionize commercial electronics in terms of new high-speed data architectures and significant reductions in overall power and weight consumption. In stark contrast, nearly all science-based interplanetary and earth-orbiting NASA spacecraft are still designing in and around mid-1980s-level non-volatile technology with 1Mb Electrically Erasable Read-Only Memory (EEPROM) devices. NASA has typically shunned the use of modern flash devices because of radiation and reliability concerns due to the commercial-offthe– shelf (COTS) nature of the NAND flash technology. Given the significant potential increases in overall system capability these modern flash devices could bring to NASA missions, it is important to continue to investigate these devices. This report will investigate certain portions of the reliability performance of NAND flash devices, specifically the disturb properties. Understanding the possible limitations such new non-volatile memory technology presents to NASA is the goal of this report.
URI: http://hdl.handle.net/2014/40761
Appears in Collections:JPL TRS 1992+

Files in This Item:

File Description SizeFormat
08-07.pdf660.14 kBAdobe PDFView/Open

Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.

 

Privacy/Copyright beacon home contact us
FIRST GOV + Div 27
+ Inside JPL
+ Daily Planet
NASA Home Page Site last updated on May 1, 2005.

If you have any comments or suggestions for this web site, please e-mail Jennifer Momjian or call 4-5540.