NASA Jet Propulsion Laboratory California Institute of Technology Follow this link to skip to the main content

BEACON eSpace at Jet Propulsion Laboratory >
JPL Technical Report Server >
JPL TRS 1992+ >

Please use this identifier to cite or link to this item: http://hdl.handle.net/2014/39667

Title: Single-event upset and scaling trends in new generation of the commercial SOI PowerPC Microprocessors
Authors: Irom, Farokh
Farmanesh, Farhad
Kouba, Coy K.
Keywords: single-event upsets
scaling trends
Cyclotron
silicon on insulator
heavy ion
microprocessors
Issue Date: 17-Jul-2006
Publisher: IEEE
Citation: IEEE Transactions On Nuclear Science, Vol. 53, No. 6, December 2006; doi:10.1109/TNS.2006.884383
Abstract: Single-event upset effects from heavy ions are measured for Motorola silicon-on-insulator (SOI) microprocessor with 90 nm feature sizes. The results are compared with previous results for SOI microprocessors with feature sizes of 130 and 180 nm. The cross section of the 90 nm SOI processors is smaller than results for 130 and 180 nm counterparts, but the threshold is about the same. The scaling of the cross section with reduction of feature size and core voltage for SOI microprocessors is discussed.
URI: http://hdl.handle.net/2014/39667
Appears in Collections:JPL TRS 1992+

Files in This Item:

File Description SizeFormat
06-2026.pdf207.17 kBAdobe PDFView/Open

Items in DSpace are protected by copyright, but are furnished with U.S. government purpose use rights.

 

Privacy/Copyright Image Policy Beacon Home Contact Us
NASA Home Page + Div 27
+ JPL Space
Site last updated on November 15, 2012.
If you have any comments or suggestions for this web site, please e-mail Alexander Smith or call 4-4202.