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Please use this identifier to cite or link to this item:
http://hdl.handle.net/2014/39405
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| Title: | On-board fault-tolerant SAR processor for spaceborne imaging radar systems |
| Authors: | Fang, Wai-Chi
Le, Charles
Taft, Stephanie |
| Keywords: | imaging Radar
synthetic aperture radar (SAR)
FPGA
fault tolerant processor |
| Issue Date: | 21-May-2005 |
| Publisher: | Pasadena, CA : Jet Propulsion Laboratory, National Aeronautics and Space Administration, 2005. |
| Citation: | IEEE International Symposium on Circuits and Systems, Kobe, Japan, May 21-24, 2005. |
| Abstract: | A real-time high-performance and fault-tolerant FPGA-based hardware architecture for the processing of synthetic aperture radar (SAR) images has been developed for advanced spaceborne radar imaging systems. In this paper, we present the integrated design approach, from top-level algorithm specifications, system architectures, design methodology, functional verification, performance validation, down to hardware design and implementation. |
| URI: | http://hdl.handle.net/2014/39405 |
| Appears in Collections: | JPL TRS 1992+
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