NASA Jet Propulsion Laboratory California Institute of Technology Follow this link to skip to the main content

BEACON eSpace at Jet Propulsion Laboratory >
JPL Technical Report Server >
JPL TRS 1992+ >

Please use this identifier to cite or link to this item: http://hdl.handle.net/2014/39285

Title: Taking evolutionary circuit design from experimentation to implementation: some useful techniques and a silicon demonstration
Authors: Stoica, A.
Zebulum, R. S.
Guo, X.
Keymeulen, D.
Ferguson, M. I.
Duong, V.
Keywords: digital circuits designs
data
compression
Issue Date: 4-Jul-2004
Publisher: IEE
Citation: IEE Proc.-Comput. Digit. Tech., Vol. 151, No. 4, July 2004 doi: 10.1049/ip-cdt:20040503
Abstract: Current techniques in evolutionary synthesis of analogue and digital circuits designed at transistor level have focused on achieving the desired functional response, without paying sufficient attention to issues needed for a practical implementation of the resulting solution. No silicon fabrication of circuits with topologies designed by evolution has been done before, leaving open questions on the feasibility of the evolutionary circuit design approach, as well as on how high-performance, robust, or portable such designs could be when implemented in hardware. It is argued that moving from evolutionary 'design-for experimentation' to 'design-for-implementation' requires, beyond inclusion in the fitness function of measures indicative of circuit evaluation factors such as power consumption and robustness to temperature variations, the addition of certain evaluation techniques that are not common in conventional design. Several such techniques that were found to be useful in evolving designs for implementation are presented; some are general, and some are particular to the problem domain of transistor-level logic design, used here as a target application. The example used here is a multifunction NAND/NOR logic gate circuit, for which evolution obtained a creative circuit topology more compact than what has been achieved by multiplexing a NAND and a NOR gate. The circuit was fabricated in a 0.5 mum CMOS technology and silicon tests showed good correspondence with the simulations.
URI: http://hdl.handle.net/2014/39285
Appears in Collections:JPL TRS 1992+

Files in This Item:

File Description SizeFormat
03-1392.pdf440.39 kBAdobe PDFView/Open

Items in DSpace are protected by copyright, but are furnished with U.S. government purpose use rights.

 

Privacy/Copyright Image Policy Beacon Home Contact Us
NASA Home Page + Div 27
+ JPL Space
Site last updated on November 15, 2012.
If you have any comments or suggestions for this web site, please e-mail Alexander Smith or call 4-4202.