|
BEACON eSpace at Jet Propulsion Laboratory >
JPL Technical Report Server >
JPL TRS 1992+ >
Please use this identifier to cite or link to this item:
http://hdl.handle.net/2014/38961
|
| Title: | VLSI design of turbo decoder for integrated communication system on a chip applications |
| Authors: | Fang, Wai-Chi
Sethuram, Ashwin
Belevi, Kemal |
| Keywords: | Very Large-Scale Integration (VLSI) Design
turbo decoder
system on a chip |
| Issue Date: | 23-May-2003 |
| Publisher: | Pasadena, CA : Jet Propulsion Laboratory, National Aeronautics and Space Administration, 2003. |
| Citation: | IEEE International Symposium on Circuits and Systems, Bangkok, Thailand, May 23, 2003. |
| Abstract: | A high-throughput low-power turbo decoder core has been developed for integrated communication system applications such as satellite communications, wireless LAN, digital TV, cable modem, Digital Video Broadcast (DVB), and xDSL systems. The turbo decoder is based on convolutional constituent codes, which outperform all other Forward Error Correction techniques. This turbo decoder core is parameterizable and can be modified easily to fit any size for advanced communication system-on-chip products. The turbo decoder core provides Forward Error Correction of up to 15 Mbits/sec on a 0.13-micron CMOS FPGA prototyping chip at a power of 0.1 watts. |
| URI: | http://hdl.handle.net/2014/38961 |
| Appears in Collections: | JPL TRS 1992+
|
Items in DSpace are protected by copyright, but are furnished with U.S. government purpose use rights.
|
