NASA Jet Propulsion Laboratory California Institute of Technology Follow this link to skip to the main content

BEACON eSpace at Jet Propulsion Laboratory >
JPL Technical Report Server >
JPL TRS 1992+ >

Please use this identifier to cite or link to this item:

Title: IBM powerPC 405 SEU mitigation using processor voting techniques in Xilinx Virtex-I1 pro FPGA
Authors: Wang, Mandy W.
Bolotin, Gary S.
Keywords: PowerPC 405
single event upset (SEU)
Issue Date: 8-Sep-2004
Publisher: Pasadena, CA : Jet Propulsion Laboratory, National Aeronautics and Space Administration, 2004
Citation: MAPLD International Conference, Washington, SC, September 8-10, 2004.
Abstract: Not until recently, Xilinx has developed a new field programmable gate array (FPGA) device family, Virtex-I1 Pro. In this single device, not only dies it have density logic cells (3K to125K), gigabit connectivity, on chip memory, digital clock management, but also it can have up to four IBM PowerPC 405 Processor hard cores, running up to 400MHz and 633 Mbps. To utilize this cutting edge device in space applications, a few Single Event Upset (SEU) mitigation techniques need to be implemented to a design for the device. At Jet Propulsion Laboratory (JPL), we have successfully demonstrated the feasibility of running multiple processors running in a lock step fashion to accomplish SEU mitigation and fault tolerance.
Appears in Collections:JPL TRS 1992+

Files in This Item:

File Description SizeFormat
04-0990.pdf1.15 MBAdobe PDFView/Open

Items in DSpace are protected by copyright, but are furnished with U.S. government purpose use rights.


Privacy/Copyright Image Policy Beacon Home Contact Us
NASA Home Page + Div 27
+ JPL Space
Site last updated on December 5, 2014.
If you have any comments or suggestions for this web site, please e-mail Robert Powers.