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|Title: ||IBM powerPC 405 SEU mitigation using processor voting techniques in Xilinx Virtex-I1 pro FPGA|
|Authors: ||Wang, Mandy W.|
Bolotin, Gary S.
|Keywords: ||PowerPC 405|
single event upset (SEU)
|Issue Date: ||8-Sep-2004 |
|Publisher: ||Pasadena, CA : Jet Propulsion Laboratory, National Aeronautics and Space Administration, 2004|
|Citation: ||MAPLD International Conference, Washington, SC, September 8-10, 2004.|
|Abstract: ||Not until recently, Xilinx has developed a new field programmable gate array (FPGA) device family, Virtex-I1 Pro. In this single device, not only dies it have density logic cells (3K to125K), gigabit connectivity, on chip memory, digital clock management, but also it can have up to four IBM PowerPC 405 Processor hard cores, running up to 400MHz and 633 Mbps. To utilize this cutting edge device in space applications, a few Single Event Upset (SEU) mitigation techniques need to be implemented to a design for the device. At Jet Propulsion Laboratory (JPL), we have successfully demonstrated the feasibility of running multiple processors running in a lock step fashion to accomplish SEU mitigation and fault tolerance.|
|Appears in Collections:||JPL TRS 1992+|
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