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Title: A hierarchical, automated target recognition algorithm for a parallel analog processor
Authors: Woodward, Gail
Padgett, Curtis
Issue Date: 10-Jul-1997
Citation: Monterey, California, USA
Abstract: A hierarchical approach is described for an automated target recognition (ATR) system, VIGILANTE, that uses a massively parallel, analog processor (3DANN). The 3DANN processor is capable of performing 64 concurrent inner products of size 1x4096 every 250 nanoseconds.
Appears in Collections:JPL TRS 1992+

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