|
BEACON eSpace at Jet Propulsion Laboratory >
JPL Technical Report Server >
JPL TRS 1992+ >
Please use this identifier to cite or link to this item:
http://hdl.handle.net/2014/11093
|
| Title: | A CMOS-compatible process technique for fabricating laterally embedded multi-nanaochannels without sacrificial etching |
| Authors: | Yang, E. Lee, C. Myung, N. George, T. |
| Issue Date: | 8-Jun-2003 |
| Citation: | IEEE Transducers 03 Boston, MA, USA |
| URI: | http://hdl.handle.net/2014/11093 |
| Appears in Collections: | JPL TRS 1992+
|
Items in DSpace are protected by copyright, but are furnished with U.S. government purpose use rights.
|